The packaging of IC chips is one of the most important steps in the manufacturing process, contributing significantly to the overall cost, performance and reliability of the packaged IC chips. As semiconductor devices reach higher levels of integration, packaging technologies, such as chip stacking in chip-on-chip devices, have become critical. Packaging of the IC chip accounts for a considerable portion of the cost of producing the device and failure of the package leads to costly yield reduction.
As semiconductor device sizes have decreased, the density of devices on a chip has increased. Along with such increases in processing power, however, has also come an increase in the amount of heat generated by the multiple chips in such chip-on-chip (or “multi-chip”) package devices. As is to be expected, excessive amounts of heat present in the package device can and typically does decrease device performance. Moreover, if the amount of heat present becomes too excessive device, damage may result.
Conventional approaches to combating the presence of heat during device operation typically include providing a heat spreading device (e.g., a “heat spreader”) in thermal contact with the IC chips in the IC package device. Usual layouts of such conventional devices have the top surfaces of the IC chips oriented away from each other, with each of these top surfaces in thermal contact with a corresponding heat spreader such that the substrates acting as the heat spreaders also provide the outer surfaces (or “lids”) of the IC package device. Unfortunately, having to provide a separate heat spreader for each IC chip can become relatively expensive, especially in IC packages having a large number of stacked IC chips. In addition, each additional heat spreader contributes to the overall size of the IC package device, which is detrimental to the continuing trend of decreased component and device sizes. Accordingly, what is needed is a technique for packaging chip-on-chip devices having efficient heat spreaders, but that does not suffer from the deficiencies found in the prior art.